Intel CPUs of the future could ‘mix and match’ different parts on the same package
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Intel CPUs of the future could ‘mix and match’ different parts on the same package
Intel is setting itself up for quite a drastic shift in chip design. At its technology and manufacturing day in San Francisco last week, the chipmaker unveiled plans for a new heterogeneous architecture that is nothing like the traditional monolithic designs we’re used to.
The new technology, which Intel is calling Embedded Multi-die Interconnect Bridge (EMIB), would allow multiple chips to be interconnected at high speeds. More significantly, it would enable different generations of chips to be featured on the same package, so the same processor could have a 22nm chip connected to a 14nm and 10nm chip.
This approach holds a lot of potential for the optimization of chips for a wide variety of workloads. “For example, we can mix high-performance blocks of silicon and IP together with low-power elements made from different nodes for extreme optimization,” says Murthy Renduchintala, Intel’s head of Client, IoT, and Systems Architecture Group.
One drawback of multi-chip packages has been the crippling latency, but the new EMIB interconnect can supposedly reduce that by up to four times and achieve speeds in the range of “multi hundreds of gigabytes”.
This would also give Intel a lot more flexibility when designing new chips, and it could theoretically build CPU and graphics cores on smaller process nodes while keeping lower performance components on larger processes.
For example, power circuits might benefit from sticking to the 22nm process, and EMIB may have helped Intel retain the fully integrated voltage regulator (FIVR) on its Skylake and Kaby Lake chips (some thought that it removed the FIVR because of trouble scaling it to 14nm).
EMIB differs from Intel’s previous attempts at fusing multiple chips in one CPU, such as with the first Pentium Pro and the Core 2 Quad processors. Those relied on wires run through the package substrate or silicon interposers between dies, and either faced speed limitations or were costly.
With EMIB, Intel could find it easier and more affordable to combine chips without sacrificing too much performance.
That said, this isn’t entirely untested technology, and it actually debuted on the Altera Stratix 10 FPGA. The crux of the matter is that Intel now plans to expand it to its other chips.
Source: Intel
