Intel will build 3D chips with its new Foveros die stacking technology
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Intel will build 3D chips with its new Foveros die stacking technology
For a long time, smaller was always better in the semiconductor industry. However, Moore’s Law is starting to look a little rusty as chipmakers struggle to shrink chips on what used to be a regular cadence.
How’s one to cram more transistors into a chip then? Intel’s answer now is to build up. The company revealed its new 3D chip stacking technology on Wednesday, dubbed Foveros. We’ve already seen chip stacking with memory, but Foveros will be the first time someone is bringing 3D stacking to CPU, graphics, and AI processors at scale.
Foveros brings the benefits of 3D stacking to logic-on-logic integration, extending die-stacking beyond traditional passive interposers and stacked memory. This technology actually follows up on Intel’s existing Embedded Multi-die Interconnect Bridge (EMIB) design, which is currently in use on the Kaby Lake-G processors that contain an Intel CPU, AMD GPU, and HBM2 memory on the same package.
Current package-on-package stacked designs take advantage of just a few hundred connections to connect things like the memory and processor in a system-on-chip, but the size and performance of the connections is quite limiting. Foveros gets around that by using etched silicon, just like EMIB, to facilitate a greater number of interconnects at higher speeds.
However, instead of EMIB’s silicon bridges, Foveros puts thousands of microbumps on the surface of chips. The underlying package also has larger solder bumps, and these have direct face-to-face connections with the stacked chips by way of Through Silicon Via (TSVs) in the silicon interposer.
Furthermore, Foveros will also involve mixing and matching different “chiplets”, where the core processor components are distributed between different dies. Better still, these chiplets don’t even have to be built on the same process. This means you could have your processor cores built on the 10nm process, while things like integrated USB, Wi-Fi, Ethernet, or PCIe could use less cutting-edge 14nm or 22nm processes.
There wouldn’t be much of a performance hit, but power usage would be a lot lower than if you used the same process across the board. Certain components like Wi-Fi or cellular connectivity are also optimized on a particular process, so the added flexibility afforded by Foveros would allow companies to use the best possible process.
This isn’t unlike what EMIB allows with its 2D integration of components built on separate processes, and the key difference is that Foveros simply adds a new level of density and builds up.
That said, the idea of using different processes for different components isn't unique to Intel. AMD has already said that its next-generation Zen 2 processors will separate the CPU logic from the I/O, where the former will be built on the 7nm process while everything else will use 14nm.
In a nutshell, Foveros lets Intel pack better performance and efficiency into smaller chip designs. It’s tight-lipped about the specifics behind that, but Raja Koduri, its new chief architect, did say that extensive testing, a new power delivery process, and a brand new insulation material did help.
The best part is that this isn't some far-flung technological innovation that we'll need to wait forever for. Intel says Foveros products will ship as soon as the second half of 2019, and that the technology is ready for mass market production. According to the chipmaker, the 2019 Foveros product will be targeted at the ultra-mobile form factor and have just a 2mW power consumption on standby.
