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AMD reveals 64-core 7nm EPYC processor based on the Zen 2 architecture

By Koh Wanzi - on 7 Nov 2018, 2:40pm

AMD reveals 64-core 7nm EPYC processor based on the Zen 2 architecture

Image Source: AMD

AMD has announced its next-generation EPYC processors codenamed Rome. The 64-core chip it previewed is designed for servers and based on TSMC’s 7nm process and AMD’s Zen 2 microarchitecture.

According to AMD, Zen 2 delivers significant improvements in performance, power consumption, and density, which can reduce data center operating costs and help companies to cut their carbon footprints by lowering the cooling requirements for the chips.

This is the first time AMD has detailed its Zen 2 architecture, and it features enhancements to AMD’s Infinity Fabric interconnect that link separate pieces of silicon within a single processor package. AMD refers to each piece of silicon as a “chiplet”, and this approach can be seen as an evolution of the modular design it introduced with the first EPYC chips.

Existing EPYC chips have up to four Zen CPU modules, but Rome will now feature multiple 7nm Zen 2 chiplets and an I/O die made using the more mature 14nm process. The I/O die will utilize Infinity Fabric interconnects to link the chiplets and eight DRAM interfaces. In addition, moving the memory controller to the I/O die also ensures that all the CPU chiplets will have more equal memory access latency.

Image Source: AMD

Furthermore, physical interfaces like DRAM and Infinity Fabric tend not to scale that well with process shrinks, so separating the CPU chiplets from the I/O die allows AMD to make the chiplets even smaller. It also enables AMD to cram in more CPU cores at the same power and is supposedly more cost-effective to manufacture than traditional monolithic chip designs.

Zen 2 is expected to include several advances as well, such as an improved and more efficient execution pipeline, better branch prediction and instruction pre-fetching, doubled floating point width to 256-bit, and hardware-based mitigations for the Spectre security flaw.

More specifically, Rome offers increased instructions-per-cycle and improved I/O and memory bandwidth. This is also the first PCIe 4.0 x86 server chip, where bandwidth per channel is doubled to boost data center accelerator performance. Compute performance per socket is expected to double as well, while floating point performance is quadrupled compared to current AMD EPYC chips.

During the Computex 2019 keynote, AMD held the first public competitive demonstration of a 2nd-Gen AMD EPYC server platform versus a 2P Intel Xeon 8280-based server running a NAMD Apo1 v2.12 benchmark test, which is for high-performance molecular dynamics simulation. The preproduction 2nd-Gen AMD EPYC processor-powered server outperformed the Intel Xeon powered servers by more than 2x on this benchmark, simulating 20ns of data that's twice as fast as the competition:-

AMD came out twice as fast as the competition in this high-performance molecular dynamics simulation test.

In a much appreciated move, AMD’s EPYC Rome processors is socket compatible with the older Naples platform and will work with AMD’s Zen 3-based Milan platform in the future. The company also confirmed that its Zen 4 architecture is on track.

Rome is sampling to customers now, with an official launch slated for sometime in 2019. 

Source: AMD

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