IDF Spring 2007 Update (Part 1)

The Year of 45nm

2007 will be the year when Intel begins its transition into 45nm process technology. Along with it, a whole slew of new products will hit the market, beginning with Intel's next generation "Penryn" processor family. The transition to 45nm, according to Intel, is a significant change to the way transistors are manufactured today as the entire transistor gate has been replaced with new silicon compatible materials.

In place of the silicon dioxide gate dielectric, Intel will use high-k Hafnium-based dielectric material. This replaces the ultra-thin silicon dioxide gate, which at 45nm, would be too thin (only a few atomic layers thick) to manufacture and unreliable. In addition to that, Intel switched the typical polysilicon gate to a full metal gate, giving it higher electrical conductivity that enables faster gate switching capabilities. These significant changes to the gate are expected to extend Moore's Law even further and it would be the materials of choice going further down into 32nm and below.

As with any transistor shrinkage, there would be significant improvement in the performance of the transistors. Already in its early sampling, Intel expects that processors built on the 45nm process would demonstrate more than 20% increase in performance and more than 10x reduction in gate leakage power. Gate leakage power reduction of 10x sounds impressive as this will determine how much heat the processor generates, and leakage is basically heat generated doing nothing. Thus, when the processor is idle and in low power state, you can expect very low heat output. In this case, we are hoping an ultra silent and cool processor.

Penryn Unveiled

The Penryn family of processors will be introduced using Intel's 45nm process technology and it will populate all segments of Intel's processor line-up. Although Penryn is still based on Intel's Core microarchitecture, Intel has tweaked the processor's architecture a little to further improve its performance. Some of the changes are shown in the chart below :-

As you can see in the highly summarized feature enhancements for Penryn, Intel has made quite a bit of changes to improve its performance. Of significance would be the very large 12MB L2 cache for its quad-core parts and 6MB L2 cache for its dual-core parts. From what we found out, it seems that Penryn would be based on a single dual-core die with a total of 6MB L2 cache. Quad-core processors would be manufactured using two silicon dies mounted on a single LGA775 chip package, similar to how it's currently done with Kentsfield. We think Intel is playing it safe by manufacturing dual-core dies rather than large quad-core dies. Since a smaller die would naturally result in higher yields, Intel chose this path to ensure that they are getting enough chips out of a single silicon wafer since 45nm is, after all, a new process. Of course, this would be significant savings to Intel as well since they would probably sell their quad-core parts at premium price while the cost of the chip is only the cost of two dual-core chips.

In addition to adding more transistors to make up a larger L2 cache, Intel is adding more instructions into the processor, in the form of SSE4. This time around, Intel is adding as many as 47 new instructions specifically targeted at improving the performance of media, graphics and gaming applications. A 128-bit Super Shuffle engine will also be introduced to improve the encoding, decoding and transcoding of high-definition video.

For future notebooks using the Penryn processor, it will benefit much with its new Deep Power Down Technology. This new method provides for an even deeper sleep state which would further reduce the power consumption of the notebook at idle state. Instead of flushing the caches of the processor in C4 state, Deep Power Down will turn off both the L1 and L2 caches to cut power usage.

Another power feature introduced in Penryn, known as Enhanced Dynamic Acceleration Technology, takes advantage of powering down one of the cores to boost the performance of the other core. This is especially useful under applications that are still single threaded (e.g. most games) and boosting the single core frequency above its specified speed would get the job done much quicker. According to Intel, the TDP under the Enhanced Dynamic Acceleration state is lower than running both cores at the same time. Thus, in addition to getting a speed boost, you consume less power at the same time. Of course, this would only be applicable with most legacy single threaded applications.

Intel Xeon MP, Tolapai & Nehalem

Pat Gelsinger, Intel Senior Vice President and General Manager of the Digital Enterprise Group detailed upcoming products in the server segment during the morning keynote at IDF. He indicated that early Penryn performance were looking great and high-performance computing (HPC) and workstation systems can expect a significant boost to their performance, with gains up to an estimated 45 percent for bandwidth intensive applications and a 25 percent increase for servers using Java.

Gelsinger also talked about Intel's high-end quad and dual-core multi-processor servers which (codenamed Caneland) will be making its debut in the third quarter of this year. These new processors will complete the line-up of Intel's Xeon processors with support for multi-processor systems. The new Intel Xeon processor 7300 series will come in either 80 or 50 watt versions for blades.

Intel also planned to release a highly integrated enterprise-class "system-on-chip" (SoC) product in 2008, codenamed Tolapai. The chip integrates several key components, such as an IA instruction set (an x86 processor), a memory controller and an I/O controller. It's basically a single chip that aims to help developers simplify system designs by reducing the chip footprint size by up to 45 percent and taking power consumption down by approximately 20 percent (as compared to a standard four-chip design). Also integrated with Tolapai is Intel's QuickAssist Technology which is a comprehensive accelerator initiative to optimize the use of accelerators in servers. Such accelerators benefit the system by optimizing the performance of certain functions, such as security encryption or financial computation. A general purpose x86 processor would not be able to handle such functions effectively and these accelerators would help boost the performance of the system while reducing power consumption.

Gelsinger also talked about the next generation of processors with the codename Nehalem. These would be scheduled for 2008 and they will come with one to eight or more cores per product. Intel indicated that Nehalem would have some sort of hyper threading like features, with each core handling up to two threads at one time. Although details were sketchy, some of these Nehalem parts would contain components such as system interconnects, integrated memory controllers and even the option for a high-performance integrated graphics engine. Nehalem would be the chip that would significantly change the platform, judging from the initial specs released during IDF.

Going further ahead, Intel would journey into 32nm chips with Westmere in 2009 and Sandy Bridge in 2010. No details were released about these future processors, except for these codenames.

Our articles may contain affiliate links. If you buy through these links, we may earn a small commission.