IDF Spring 2006 - Next Generation Microarchitecture Revealed

Opening Keynote

Justin Rattner's opening keynotes today was a half-hour run through on Intel's new focus on energy efficiency as evident in this year's theme of "Power-Optimized Platforms". Rattner talked about energy being the critical focus in Intel today, be it in high-density data centers, thin and light notebooks or even in handheld devices.

Parallels were drawn with the automotive industry, where there is an eternal power struggle between performance and energy consumption. You either have high-speed vehicles that guzzle fuel, or long distance fuel economy, but less-than exciting speeds. Rattner then revealed that Intel has been facing the same problems with microprocessor ramping, detailing how energy use has quadrupled over the past decade beginning from the original Pentium till today's Pentium 4. "Every increase in performance required an intended increase in energy expended", Rattner said. The new buzzword thrown about today was 'Energy-per-instruction' or the amount of energy required to execute a single instruction in a processor.

When Intel first introduced the Pentium M around 2003, they developed a mobile processor that was able to match the energy efficiency that the original Pentium exhibited back in 1993. Of course, we all know that mobile processors are unable to match the performance of desktop systems and Intel's deeply pipelined and power hungry NetBurst microarchitecture just went to prove that they were going the wrong way. This was one of the areas Intel has been facing tough challenges from AMD.

The push towards multi-core technologies and the launch of the Yonah (Core Duo) processor and Napa (Centrino Duo) platform were the first steps to delivering best-in-class performance with great energy savings. Today Rattner finally revealed the details about Intel's long talked about Next Generation Microarchitecture - what has now been christened as the Intel Core microarchitecture (somehow, we saw that coming). The Core microarchitecture will make its debut with the 65nm Merom, Conroe and Woodcrest processors by Q3 this year and will be the pervasive microarchitecture across all Intel platforms then.

Intel Core Microarchitecture

Intel Core microarchitecture details have been unveiled and it's more than just pipeline optimizations. The five main features that make up the Core microarchitecture are listed below.

• Intel Wide Dynamic Execution - Delivers more instruction per cycle. While featuring a shorter 14-stage pipeline, the Wide Dynamic Execution engine will come with a deeper 4-issue width execution cores. It will also feature the Pentium M's Micro-fusion function, low-level technique to fuse two micro-ops into a single micro-op to improve performance.

Core microarchitecture will introduce a new feature called Macro-fusion, similar to Micro-fusion, but fusing instead 2 higher-level x86 instructions into a single instruction, thus increasing performance again while being more efficient.

• Intel Intelligent Power Capability – With fine-grain power control and power-gating, the Core microarchitecture will build on Yonah's energy saving features with the ability to turn down individual processor cores and manage L2 cache on demand.
• Intel Advanced Smart Cache – All Core microarchitecture processors will feature the advanced smart cache capabilities we first saw in the Core Duo (Yonah), including a shared L2 cache and dynamic cache allocation. However, L2 cache will also be doubled to 4MB in total.
• Intel Smart Memory Access – The key feature here is called 'memory disambiguation', which is an intelligent speculative memory technology to enable execution cores to perform a 'load' command on the next set of data before previous 'store' instructions have been executed.

Core microarchitecture will also have advanced pre-fetch techniques to optimize memory access bandwidth and reduce latency.

• Intel Advanced Digital Media Boost – Improvements were made to SSE/SSE2/SSE3 instruction execution, which is now capable of single-cycle 128-bit SSE execution, effectively doubling performance (clock-rate wise as Intel was quick to point out) of SSE instructions.

Keynotes aren't really the platform to extract really detailed information about the Core microarchitecture, but Rattner did provide the projected returns on performance and the energy savings we will see when Merom, Conroe and Woodcrest are launched around Q3 this year. With the new Core microarchitecture, Merom would exhibit a 20% performance gain over a comparable Core Duo processor (T2600 was used as an example) while keeping battery life constant. In any case, the myth about Merom being nothing more than a Yonah (Core Duo) with 64-bit can now be laid to rest.

Conroe desktop processors are predicted to exhibit a good 40% performance increase over a similar Pentium D 950 while reducing power consumption by 40% as well. Finally, the server-side Woodcrest will feature the biggest jump in performance as Rattner claims up to 80% performance gains with a 35% energy saving compared to a relative Xeon 2.8GHz with 4MB L2. Now if these numbers are to be believed, the second half of 2006 may very well swing back into Intel's favor.

Why Multi-Core

Rattner's keynote continued with a sort of 'debunking the myth' presentation on why multi-core is the future of computing. Why push for multi-core now? Again energy became the key focus and not performance per se. Rattner gave a simple explanation that the power required to ramp up a single core processor does not scale well with the performance gains. Yes it can be done, but you could possibly be increasing power by 70% for mere 13% gains. Instead, Intel turned towards downclocking the processor, reducing power by 50% and found out that the reduced frequency would only relate to a 13% performance loss. However, because the power consumption is now so low, slapping on a second core would basically only bring up the power levels to where it was originally, but featuring two execution cores for a much better performance gain.

The illustration given was a very simple example using static and unconfirmable figures, but we find it effective to get the message across on how multi-core technology is helping to increase performance while keeping the power envelop low or in check. The same concept is then applicable to quad core and beyond.

Power-Optimized Platforms

With the Core microarchitecture and multi-core technologies, Intel has reached a milestone in delivering energy efficiency on the microprocessor level and thus they begin their focus on the next level of power optimization and that is to look at power-optimized platforms. Rattner continued his keynote speech detailing how platform power consumption will now be Intel's next challenge, effectively trying to squeeze more energy efficiency from the platform level. "Processor power is only a third of total platform power, while the rest of the platform is dominating energy consumption", Rattner stated. Because of this, Intel is looking into ways to further increase idle mode efficiency and one of the methods in research now is the Display Self-Refresh.

Rattner then showed a prototype design for Ultra-Mobile PCs called the Silverton platform, which has experimental platform power saving features built in. On idle, the platform runs at about 6.5W and with extended I/O mode enabled, the platform power consumption has been reduced to 3.5W, but loses none of its responsiveness. Power was then cut off to the motherboard, so that they could demonstrate the Display Self-Refresh mode, which kept the monitor up, but now energy consumption has dropped to 1W. We'd like to remind you that these are basically proof-of-concept demonstrations by Intel into their efforts in developing Power-Optimized Platforms, so don't be expecting the upcoming Santa Rosa, Bridge Creek or Averill platforms to run on 1W idle.

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