We visited the factory that assembles Intel's next-gen Meteor Lake CPUs

Production Stage 1 and 2

Note: This feature was first published on 11 September 2023.

The magic of planet-scale orchestration, the Intel way

Did you know there's a whole chain of complex processes beyond wafer production at wafer fab plants to transform them into processors used in laptops and servers? Most tech publications like ours often focus on the wafer fab capabilities as they dictate the output possibilities for meeting the industry's needs. However, there are four other vital stages beyond wafer fabrication that help get processors out to consumers and businesses that are not often discussed.

Chiefly, they are the advanced packaging stage, die prep and die sorting, die assembly and testing, and finally, board and system-level integration testing. While Intel's homeland, USA, has several wafer fab plants, most of the packaging, assembly and testing phases occur across overseas sites. Of them, Malaysia is the company's very first offshore site from way back in 1972.

Fifty-one years later, it is home to 15,000 employees with over 900,000 square feet of manufacturing capacity in Penang. Its current and upcoming facilities are capable of handling all the stages after receiving a silicon wafer. It is also home to the design and development stages of Intel's next-generation Meteor Lake processors, including its high-volume manufacturing.

We expect Meteor Lake-based processors (also otherwise fondly referred to as the 14^th Gen Core processor) to be formally announced at Intel’s upcoming Innovation event and show up in laptops by the end of this year. This is why Intel took the opportunity to gather the world’s top tech publications (like HardwareZone, of course) and analysts to showcase what they are capable of at Intel’s Penang factories ahead of the official announcement. It is also the very first time that Intel is opening up its Penang factories to the press at such a large scale and with broad access to most of the critical stages that processors undergo to convert them into their final form – be it shipped off to laptop manufacturers, or to be boxed up for retail sales. As such, we truly appreciate the access and logistics they’ve arranged to make the Intel Tech Tour Malaysia such an eye-opener.

In essence, the Intel Penang operations play a vital role in upholding Intel’s IDM 2.0 leadership plan (where IDM stands for Integrated Device Manufacturer) outlined by CEO Pat Gelsinger to uplift the internal factory network and support at-scale manufacturing in-house. Intel has already invested billions into its Penang factories, but they are not stopping anytime soon.

While up to US$20 billion is being invested for new fabs in Arizona, USA, to bolster wafer production and to serve up its chip manufacturing services to others via a new Intel Foundry Services branch (again, part of IDM 2.0), they’ve also shared not long ago that Intel is investing a further US$3.5 billion in New Mexico, USA, for advanced packaging facilities, as well as a further US$7 billion in Intel Penang for both packaging and testing facilities among others to come. By 2032, Intel estimates that they will have invested a total of US$14 billion in their Malaysia operations. Once these added facilities are up and running, Intel Penang’s manufacturing space will increase just over two-fold to over 2 million square feet.

Those are no small figures or processes, so what exactly happens in Malaysia after Intel sends over its silicon wafers? Here's a 60-second overview in our TikTok reel, but read on for the titillating details.

@hwztech We're just weeks away from Intel's next-gen CPU launch, so Vijay is at Intel #Penang factories to see if he could sneak one out! #intel #inteltechday #inteltechtour #meteorlake #cpu #processor ♬ Flowery Resale - DJ BAI

Stage 1: Die Prep and Die Sort

After the wafers are dispatched from the fab, they are sent to suitable processing facilities worldwide to prep and sort the dies that are etched on thsoe wafers. The Kulim Die Sort and Die Prep (KMDSDP) in Malaysia is one such processing facility.

300mm wafers are the standard size produced these days, and they are received at Kulim, where they are singulated into individual chips via a series of processes.

This involves grinding (thinning the wafers to suit the target profile such as certain mobile devices), die separation via precision laser scribing, followed by mechanical cutting using diamond-tipped blades to perform the cut while having chilled water flowing over them to regulate the necessary temperatures to prevent expansion, warping and clearing the cut debris. As with any other factory tour, we weren’t allowed to film on our own devices and had to rely on Intel-certified media for sharing. Unfortunately, there wasn’t a suitable media to showcase what we’ve just mentioned. Still, we can tell that all these are done with surgical precision thanks to advanced robotics and sensors working in unison.

The individual chips are then placed into transfer media, which move onto subsequent sort operation. In this process, the chips are tested to check for defects and measure their performance. To achieve this task, every chip is tested by a bus-sized sort module comprising 20 individual test cells.

This is where the dies are tested, sorted and characterised by their capabilities via lots of electrical signal testing. Most tests are conducted autonomously with die lots ferried by automated guided vehicles (AGVs) and fed into a suitable test bank, which can self-manage and test each die from the tray of dies supplied. These ‘self-roving ferries’ lower staffing needs and rule out human errors throughout the cycle. However, at all times, lab technicians and specialists are in the loop via monitoring stations spread throughout the floor to oversee several testing modules and their status.

Each chip is tested on a probe card, which interestingly contains thousands of fine needles thinner than human hair and connect to the integrated circuit inside the test equipment. This helps measure the electricity of the chip circuits for reliability and defect analysis.

Once tested and sorted, the chips are placed onto different reels associated with their capabilities (kind of like how they derive SKUs), with tape layers protecting the dies for safe transport to the Assembly and Test factories of the next stage to transform them into a fully completed processor.

Stage 2: Advanced Packaging (Assembly Phase One)

Chip reels arrive at Assembly and Testing facilities like Penang (PGAT) to be prepped for advanced packaging. This is an additional stage in chip manufacturing where processors designed for Intel’s Foveros packing technology will first be sent for wafer-level 3D packaging (also known as Advanced Packaging) before being attached to a PCB substrate and attaching its heat spreader.

The upcoming Meteor Lake processors are designed to use Foveros 3D die-stacking technology, and it’s a big deal. This advanced packaging type allows Intel to use disaggregated architectures to assemble a processor by matching the right process technology to be applied to different processing blocks. Intel will no longer be tied to managing a single, complex, monolithic design, allowing a radical re-architecture of the processing blocks. Intel has hinted previously that Meteor Lake will be using various dies or tiles packaged densely over a silicon wafer interposer (or base tile). This is precisely what the Advanced Packaging process oversees– prep individual dies for each product as required and assemble and connect them onto the base wafer.

Stacked designs aren’t new, but the problem with existing package-on-package methods is that they only have a few hundred connections to connect things like the memory and processor in a system-on-chip solution. Foveras 3D packaging provides a very high-density bump count, maintains high efficiency and delivers extremely low latency – all of which are essential proponents to help embrace a high-speed disaggregated architecture with increasingly high bandwidth demands. We first reported about Foveros here and with comparisons to EMIB. You can check out the Intel video embedded above that better illustrates how Foveros helps build a new class of processors. (Disregard the additional EMIB packaging step, as it won’t apply to Meteor Lake. This clip was produced for their workstation Intel 4th-gen Xeon Scalable processor codenamed Sapphire Rapids, launched earlier this year and uses both Foveros and EMIB to manage this complex chip.)

Intel Malaysia’s expansion plan involves building a brand-new Advanced Packaging facility, codenamed Pelican, which is underway, but the tools required to manage Meteor Lake processor assembly are already present within their existing factory area. This is yet another critical reason why Intel has gathered tech journalists to show that Intel means business with their IDM 2.0 plan that’s in full swing.

Following this stage for Advanced Packaging, the 3D stacked wafer would go through a singulation process to carve out the singulated die (which we covered in the Die prep and Die Sort stage) before being ferried to the next phase of Assembly and Testing for its final packaging process. Head over to the next page to see how the dies finally get to be completed processors!