IDF Fall 2006 Update (Part 1)

Tera-Scale Computing

Intel Developer Forum opened today with talks about Intel's next leap into Tera-Scale computing. Intel President and CEO Paul Otellini revealed a new research prototype processor that has 80 floating point cores all packed in a single 300mm² die. The prototype chip is capable of achieving a Teraflop of performance.

According to Intel Senior Fellow and CTO Justin Rattner, the rise of mega data centers delivering services such as photo-realistic games, share real-time video and multimedia data mining will challenge the industry to deliver TeraFLOPs of performance and Terabytes of bandwidth.

Although still in the early stages of research, the prototype chip will allow Intel to study the architecture of the multi-core chip and test interconnect strategies between chips and between cores and memory. "While any commercial application of these technologies is years away, it is an exciting first step in bringing tera-scale performance to PCs and servers," said Rattner.

What's interesting in this prototype design is that each of the cores are actually connected to a separate SRAM memory chip, making it possible for the entire chip to deliver more than a terabyte-per-second of bandwidth. This is achieved by stacking a memory die fashioned in the same 8x10 block array as the cores. The memory die is then bonded to the processor die through thousands of interconnects. Think of it as a flip-chip bonding process, but only that this time it's done on top of another chip. In order that the entire stacked chip makes communication to the outside world, deep through-hole vias will be fabricated on the memory die, so that a second flip-chip connection can be made to the chip package.

Besides that, each of the cores will also be equipped with an internal router that moves data between cores for load balancing purposes. According to Intel, these routers will have built-in intelligence, so much so that if it detects an overworked core, it will not route workloads to the core and if a core within the array failed, it will intuitively route work to spare/redundant cores, so that the tera-scale chip will continue to perform within expectations. Some of these ideas will be investigated with the prototype although it's likely that most of them may actually end up in the final design.

Taking a broader overview of the tera-scale chip, we can see very familiar ideas being thrown into the prototype. Here we have built-in memory controllers for fast local memory access and chip-to-chip communications. Both of these technologies are already in existent today with AMD's chips although they are far less advanced than what is being tested by Intel. However, what's important to note is that Intel is recognizing the fact that in order to move huge amounts of data, either to memory or to other cores, such an architecture is inevitable. However, it is likely that Intel will only start to embrace this with multi-core chip designs.

Silicon Photonics Breakthrough

In order to complement future tera-scale computers, optical interconnects are needed to provide high speed delivery of massive chunks of data either between racks, boards or even between chips. As the industry begins to meet technological limits at the copper level, Intel is investing in a somewhat unique approach to bring optical connectivity at the silicon chip level.

Today, Intel revealed yet another silicon photonics breakthrough. Working with a research team at UCSB (University of California Santa Barbara), Intel unveiled the first electrically pumped hybrid silicon laser.

The hybrid silicon laser is achieved by coupling an indium phosphide laser with a silicon waveguide. Since both indium phosphide and silicon are largely different types of material, these two components were 'glued' together by growing a thin 25 atom thick oxide layer using an oxygen plasma process and then fused together through a low temperature process. This simple processing method makes volume manufacturing of silicon lasers possible since both materials are separately processed. Previous attempts by other researchers to directly grow indium phosphide on silicon have been unsuccessful as the largely different material properties caused crystal lattice mismatch and poor lasing performance.

Now that an electrically pumped hybrid laser has been proven as a viable option, Intel looks set to integrate all the other components (e.g. modulators, waveguides, multiplexors/demultiplexors) into a single silicon chip.

Intel expects this breakthrough to be a stepping stone to future silicon based optical devices manufactured at high volumes and available at low cost. It is also an Intel vision to integrate optics into future tera-scale computers by using low cost optical interconnects on a board-to-board level (like in a blade application) or even between high performance multi-core chips.

All I Want For Christmas Is... Quad-Core

Intel confirmed their commitment to deliver quad core by the end of this year and they are determined to ship the first quad core processor for both the desktop and server segment sometime in November.

On the desktop side, the new quad core processor, codenamed Kentsfield, will make its debut in the extreme segment with the new Intel Core 2 Extreme Processor QX6700. It will be based on the 65nm process technology and will use two dual core dies mounted on the same chip package. This means that both chips will share a common bus and it will have a total of 8MB of L2 cache. However, not all of the L2 cache are shared since both the dies are not interconnected. Each pair of cores will share 4MB of L2 cache. No pricing has yet been released although Intel indicated that their pricing strategy for the new extreme quad core processor will be similar to how they priced all of their previous Extreme Edition processors. The processor will be clocked at 2.66GHz (at 1066MHz FSB), frequency slightly slower than the dual core Core 2 Extreme X6800. Intel says that the X6800 will remain in the roadmap until the mid of 2007 as they believe that it will continue to serve a different usage model, mostly for gamers who want high speed performance for today's mostly single threaded applications. The Core 2 Extreme QX6700, on the other hand, will be ideal for those using it with highly threaded high definition video editing or CAD/CAM applications.

The Core 2 Extreme QX6700 is expected to boost performance by as much as 70% in highly threaded applications as compared to the Core 2 Extreme X6800. Kentsfield will work with most Conroe-compatible boards although a new BIOS update would be needed. However, power consumption for the new quad core processor will double to 130W since it is essentially made up of two Conroe processors. The mainstream parts, clocked at lower speeds, will be rated at 100W.

By early 2007, expect quad core processors to move into the performance and mainstream desktop segment. The model number has not yet been revealed but we know that it will be clocked at 2.40GHz running at 1066MHz FSB.

There were also hints of a new desktop chipset next year although details were not revealed. We do know, however, that the chipset will feature support for new DDR3 memory. DDR3 will continue to boost memory bandwidth past the 800MHz limit, the highest speed achievable by current DDR2 modules (not considering limited overclocked memory parts that scaled it beyond the 1GHz mark). At the show floor, both Micron and Samsung are already sampling DDR3 modules, ranging from unbuffered desktop modules to SO-DIMMs for notebooks.

Upcoming Quad-Core Desktops

We saw a couple of very beautiful and interesting gaming systems based on Intel's upcoming Core 2 QX6700 processor. The following are some that caught our attention.

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