The Hybrid Memory Cube Consortium (HMCC) has announced its new DRAM memory architecture, called the Hybrid Memory Cube (HMC) technology, which is touted to improve performance over standard DDR3 and DDR4 DRAM while simultaneously reducing power consumption.
One of the key improvements allegedly made by HMC technology is the ability to remove memory bandwidth bottlenecks that is due to the limitations of the width of the memory module's interface as well as its operating frequency. HMC technology hopes to overcome with its revolutionary stack of through-silicon-via (TSV) bonded memory die that is coupled with a "high-speed logic layer". This stacked bonded memory die seems very similar to the future generation Volta GPU that features stacked DRAM where the video memory chips co-exist on the same silicon strata as the Volta GPU to increase its memory bandwidth to 1TB/s.
Compared to the Volta GPU, the HMC's current maximum theoretical bandwidth peaks at 160GB/s, which is roughly ten times more than a DDR3-2133 memory module; however, the consortium aims to double that to 320GB/s in the future. Besides increasing the bandwidth, the HMC technology is touted as being able to optimize power efficiency with its scalable "Far Memory" implementation.
Also, with its stacked design, the HMC technology also allows more memory to be installed in each machine, and takes up less space as well. This new technology is supported by members of the HMCC that include Marvell, Micron Technology, National Instruments, Open-Silicon, Samsung, SK Hynix, and ST Microelectronics.
The HMC Specification Version 1.0 was developed by the HMC Consortium in over seventeen months; its next version is targeted to be finalized by first quarter of 2014. Hence, we may be able to see HMC-based memory products by this year before its current specification is updated. For more information, please visit HMCC's site.
(Source: Hybrid Memory Cube Consortium)