Details of New Steamroller Microarchitecture Revealed by AMD CTO

Details of New Steamroller Microarchitecture Revealed by AMD CTO

Last week, AMD CTO, Mr. Mark Papermaster, delivered a keynote speech at the Hot Chips conference held in Silicon Valley. He detailed the new Steamroller microarchitecture and its key enhancements over the Bulldozer, the incumbent microarchitecture.

From the looks of block diagram of Steamroller, it is very similar to that of Bulldozer as the new microarchitecture is based on the latter. On closer inspection, there are a pair of decoders for Steamroller while Bulldozer has a shared decode amongst the schedulers; both integer and floating point ones. Tech Report speculated that the shared decoder of the Bulldozer microarchitecture may be the main culprit for its lackluster single-core performance.

Another improvement of Steamroller over its predecessor is said to be its power efficiency that is due to the introduction of a "...dynamically resizable L2 cache.". The Steamroller module is able to resize its L2 cache by powering down cache's unused blocks, based on its hit rate. During his presentation, AMD CTO also talked about the power efficiency gains from improved designed methods of Steamroller, using a "...high-density cell library...".

Mr. Mark Papermaster also talked about the AMD Freedom Fabric technology that will link multiple processors and system modules with a 160Gbps Ethernet uplink connection, to access a pool of shared storage, for virtualized I/O operations. It even claims to be independent of instructions set architecture. This promised technology will effectively take cloud computing to a new level that AMD has labeled Surround Computing. With this new Steamroller microarchitecture and its supporting interconnect technology , AMD said that they are poised to enter this new era of Surround Computing.

(Source: Hot Chips via Tech Report, AMD)

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