ASUS PhysX P1 GRAW Edition 128MB (PCI)


The PhysX Hardware

The PhysX Hardware

Being a newcomer to a gaming scene dominated by graphics titans and potential competitors like ATI and NVIDIA, Ageia is understandably coy about its hardware, with most of the technical details buried in patent legalese. The datasheet provided to us by ASUS is rather thin on the details but here's what generally known about the PhysX hardware:

  • Manufactured by TSMC on a 130nm process
  • 125 million transistors
  • 32-bit PCI bus
  • 128-bit GDDR3 memory interface
  • 12GB/sec memory bandwidth
  • 128/256MB memory capacity (currently only 128MB versions)
  • 733MHz memory clock (Samsung 2.0ns rated chips)
  • Sphere-sphere collisions/sec - 530 million maximum
  • Convex-convex collisions/sec - 533, 000 maximum
  • 20 billion instructions/sec
  • Total power consumption of around 28W

Browsing through the online patent application , one can make out (despite the dense language) that the PPU comprises of three main components internally. First, there's the PPU Control Engine (PCE) that is obviously the brains of the outfit, responsible for directing the flow of data between the system CPU and the PPU. Then there is a Data Movement Engine (DME) that's in charge of moving data to and from the internal and external memory, hence keeping the floating point processing units happy and well fed with data. Finally, there is the actual workhorse of the PPU, the Floating Point Engine (FPE) consisting of multiple vector processing units capable of performing multiple floating-point operations that form the majority of the mathematical calculations used in physics simulation.

Communications between the PPU and the rest of the system are transmitted through the PCI bus, (though the patent seems to cover all possibilities including other protocols like USB and PCI Express) which despite not being the fastest of interfaces, does have an advantage of being commonly found in most motherboards, old and new. An interesting fact is that with the advent of the PPU, an additional layer of interaction is present, as instead of the former CPU-GPU two-way communication, you'll now have CPU-PPU-GPU. There could be latency issues involved here though again the patent allows for a future implementation where the PPU may be integrated with the GPU on a single board or even on the motherboard, which may alleviate such concerns.