IDF Spring 2006 - Next Generation Microarchitecture Revealed

Intel Core Microarchitecture

Intel Core Microarchitecture

Intel Core microarchitecture details have been unveiled and it's more than just pipeline optimizations. The five main features that make up the Core microarchitecture are listed below.

"Together they deliver outstanding performance, not just in mobile platforms where it originated, but across all platforms." - Justin Rattner, Intel Chief Technology Officer

  • Intel Wide Dynamic Execution - Delivers more instruction per cycle. While featuring a shorter 14-stage pipeline, the Wide Dynamic Execution engine will come with a deeper 4-issue width execution cores. It will also feature the Pentium M's Micro-fusion function, low-level technique to fuse two micro-ops into a single micro-op to improve performance.

Wide Dynamic Execution.

Core microarchitecture will introduce a new feature called Macro-fusion, similar to Micro-fusion, but fusing instead 2 higher-level x86 instructions into a single instruction, thus increasing performance again while being more efficient.

Example of Micro and Macro-fusion instruction optimizations in the Core microarchitecture.

  • Intel Intelligent Power Capability – With fine-grain power control and power-gating, the Core microarchitecture will build on Yonah's energy saving features with the ability to turn down individual processor cores and manage L2 cache on demand.
  • Intel Advanced Smart Cache – All Core microarchitecture processors will feature the advanced smart cache capabilities we first saw in the Core Duo (Yonah), including a shared L2 cache and dynamic cache allocation. However, L2 cache will also be doubled to 4MB in total.
  • Intel Smart Memory Access – The key feature here is called 'memory disambiguation', which is an intelligent speculative memory technology to enable execution cores to perform a 'load' command on the next set of data before previous 'store' instructions have been executed.

Memory Disambiguation is a new feature for Core microarchitecture memory optimization.

Core microarchitecture will also have advanced pre-fetch techniques to optimize memory access bandwidth and reduce latency.

  • Intel Advanced Digital Media Boost – Improvements were made to SSE/SSE2/SSE3 instruction execution, which is now capable of single-cycle 128-bit SSE execution, effectively doubling performance (clock-rate wise as Intel was quick to point out) of SSE instructions.

Keynotes aren't really the platform to extract really detailed information about the Core microarchitecture, but Rattner did provide the projected returns on performance and the energy savings we will see when Merom, Conroe and Woodcrest are launched around Q3 this year. With the new Core microarchitecture, Merom would exhibit a 20% performance gain over a comparable Core Duo processor (T2600 was used as an example) while keeping battery life constant. In any case, the myth about Merom being nothing more than a Yonah (Core Duo) with 64-bit can now be laid to rest.

Projected Woodcrest performance gains over current Intel Xeon processors with Core microarchitecture.

Conroe desktop processors are predicted to exhibit a good 40% performance increase over a similar Pentium D 950 while reducing power consumption by 40% as well. Finally, the server-side Woodcrest will feature the biggest jump in performance as Rattner claims up to 80% performance gains with a 35% energy saving compared to a relative Xeon 2.8GHz with 4MB L2. Now if these numbers are to be believed, the second half of 2006 may very well swing back into Intel's favor.

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