IDF Fall 2006 Update (Part 2)


SSE4, Geneseo, Intel's FSB Licensing

Intel Talks SSE4

Intel also announced plans to add more than 50 new SSE4 (Streaming SIMD Extensions 4) instructions into the current Intel 64 instruction set architecture in their next generation of processors. Revealing all the new instructions in a new white paper released at IDF, Intel intends to get developers ready to take advantage of SSE4 when it launches. The new SSE4 instruction set will go into the next generation 45nm processors slated later in 2008.

Besides SSE4 which benefits multimedia and gaming , there will also be new Application Targeted Accelerators that will provide a new foundation for delivering low-latency, lower power fixed-function capabilities. The first set of application targeted accelerators will accelerate the cyclic redundancy check (CRC) of several data integrity applications. The new CRC instruction will bring performance advantage to targeted network protocols like iSCSI and RDMA (Remote Direct Memory Access) without adding additional cost.

The second application targeted extension will accelerate searches involving large data sets. Applications such as those involving genome mining, handwriting recognition, digital health workloads and fast hamming distance/population count will benefit from this extension.

Intel Talks Geneseo

Intel, along with IBM, proposed the next generation of PCIe which will be designed and optimized primarily for graphics and advanced I/O applications. Working with the codename "Geneseo", the PCIe standard will be extended to allow tasks like visualization and media processing, math intensive data crunching and content processing faster and more efficient than existing add-in cards or software approaches.

Basically, Geneseo proposes to improve platform performance through four areas and will eneable Geneseo accelerators to :-

  • use the existing PCIe architecture to initialize and manage devices
  • streamline application-to-accelerator interactions
  • and reduce system and software latency and overhead.

The industry is expected to make Geneseo work on existing industry interfaces for board and slot form factors. As such, it is expected that Geneseo will be compatible with current PCIe.

Intel Licenses Its Front Side Bus

Similar to AMD's Torrenza efforts to open up the HyperTransport architecture and AMD's unique Direct Connect Architecture to allow the development community to develop products that uses their unique bus technology, Intel too is licensing its front side bus technology to select vendors like Altera and Xilinx. These two FPGA vendors will be able to create FPGA products that use Intel's front side bus, enabling developers to use these FPGAs on current Intel platforms. It will take a while before Xilinx and Altera starts shipping FPGAs, and even longer before the development community begins to build anything out of it.