Intel's Silverthorne, Tukwila Updates and More


Silverthorne Details Revealed

Silverthorne Shapes Up

At the International Solid State Circuits Conference held at San Francisco, Intel presented 14 new technical papers that revolved around ultra mobile wireless computing, wireless radio technology standards and Tera-scale computing project. In this article, we'll be summarizing the most significant updates presented.

First up, Intel revealed more information on its processor technologies. Designed for ultra mobile computing, Intel spent a good deal of time relating how Silverthorne processors on the "Menlow" Mobile Internet Device (MID) platform are going to usher in a whole new segment of devices. Silverthorne is a low-powered Intel-Architecture (IA) processor that's derived from the Core 2 Duo desktop processor, thus conforming to the full C2D Instruction Set Architecture (ISA), but it consumes far lower power than even the ultra-low-voltage (ULV) Core Solo/Duo processor. Based on the same 45m high-K metal-gate CMOS transistor design as was the desktop Penryn processors, this 47-million transistor chip is designed for sub-1W to 2W operation - something that even the lowest powered ULV Core Solo processor cannot attain as it has trouble hitting the 5W barrier. To further conserve power, the processor uses a split I/O power supply to allow certain sections of the chip to shut down when not required. Other power management techniques incorporated is a Deep Power Down (C6) state, clock gating and power optimized register file to further curb dynamic and leakage power.

The Silverthorne is a dual-issue in-order 16-stage pipeline architecture with Hyper-threading (HT) support. Note that all current mainstream Intel processors are using out-of-order architectures, but on a processor of its scale/use and its limited resources, Intel opted for a more streamlined approach with lower analysis overhead. In case you're wondering why Hyper-threading is again making a comeback, the Silverthorne is a single-core processor and the best way to utilize its already limited resources effectively is via SMT type of Hyper-threading. Another reason HT was incorporated was because it required very little more silicon/logic to greatly increase efficiency. When HT first came to the consumer level several years ago, we've already seen its benefits of resource optimization through parallelism. This worked marvelously on single-core processors but has lost its advantage in the current multi-core processor era. As such, the Silverthorne is a single-core processor with dual-thread handling capability.

As for the status of the Silverthorne processors, Intel is already sampling them for production and their schedules are on track for introduction in the first half of this year. While Intel can't yet comment on the exact specifics of the chip details, performance at the moment is estimated to be around the same class as that of the first generation Pentium M processor (Banias core). This is based on Silverthorne's single-thread operation and it should fare slightly better with HT. Considering that Silverthorne processors are destined for ultra mobile computing devices such as UMPC-type devices and perhaps even Smartphones, that sounds like a lot of juice for very decent power draw. One of its most formidable opponents is none other than Samsung's ARM processor series, but we'll reserve true judgment when appropriate gadgets are made available utilizing the Silverthorne processor. Currently, the Intel A100 and A110 ultra mobile processors are using the Stealey core that's derived off the original Pentium M core. Silverthorne and its Menlow platform will replace them once they debut.