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Intel's CPU Roadmap: To Nehalem and Beyond

By Vijay Anand - 21 Mar 2008

Nehalem's QuickPath & Integrated Memory Controller

Nehalem's QuickPath & Integrated Memory Controller

Similar to AMD's use of HyperTransport links for high-speed point-to-point inter-component or processor connectivity/communications, Intel has developed its own version called QuickPath Interconnect (QPI for short) and works very much the same was as HyperTransport links on the AMD platform. QPI itself, is part of the QuickPath architecture that integrates the memory controller in to the processor while relying on QPI for inter-processor and inter-component communications (e.g. the I/O Hub). As such each processor directly interfaces with a pool of physical memory and while in a multi-processor setup, each processor can communicate between one another to use various memory banks. As such, you can see why this is termed a NUMA platform/processor architecture. Talking about multi-processor communications, you can already tell that Intel plans to introduce this to the workstation/server market, but being scalable in nature, it can also be used in a high-end uni-processor setup for desktops. Here's a diagram as to how Nehalem will be implemented on both platforms:-

Be it for Servers or high-end desktop system implementation, Nehalem was design with scalability in mind, just like the AMD Opteron and Phenom series. Also seen here is the codename for the new Tylersburg I/O hub that will be used in conjunction with the Nehalem architecture. A separate ICH hub will still exist to provide Intel various building blocks for the broad range of platforms that Nehalem will take on.

Here are some key points of the Nehalem microarchitecture with regards to the Intel QuickPath Interconnect and the core's integrated memory controller:-

Intel QuickPath Interconnect

  • Two QPI links will be present per CPU socket in the first implementation of Nehalem. Number of QPI links can be increased or decreased as required for the market designation in future CPU revisions as the QPI is one of the extensible building blocks of the Nehalem CPU architecture and not something tied down to the core per se.
  • QPI uses up to 6.4 Gigatransfers/second links, equivalent to delivering a total bandwidth of up to 25.6Gb/s per link - vastly faster than AMD's current solutions, but that's not to say it's inferior as its bandwidth can be scaled up as well. Intel's QPI transfer speeds aren't set in concrete yet, but the figures listed here show its capabilities.
  • Built in reliability, availability and serviceability (RAS) features ensure high reliability of QPI. Examples of these are link-level CRC, self-healing links that avoid error prone areas to reconfigure themselves to use the good parts of the links, and automatic clock re-route function to data lanes in the event of a clock-pin failure.
  • QPI even has hot-plug capability to support hot-plugging of nodes such as a processor card for example.

Nehalem's Integrated DDR3 Memory Controller

  • Nehalem processors will come integrated with a new integrated DDR3 memory controller that's not a dual-channel controller, but a tri-channel controller! Therefore total memory bus width goes up from 128 bits to 192 bits.
  • The memory controller itself has a maximum memory bandwidth handling capacity of 64GB/s which is massive. With the memory controller integrated on the processor, it communicates directly with the physical memory array and thus drastically reduces memory latencies.
  • The controller supports both registered and unregistered memory DIMMs.
  • Supports DDR3-800, DDR3-1066, DDR3-1333 JEDEC standards and has room for future scalability. No additional information was shared as to how future standards will be supported. However with the memory controller able to handle 64GB/s, a full tri-channel DDR3-1333 implementation will only amount to 32GB/s maximum bandwidth utilization. Even DDR3-2000 will not max out the controller, so we hope future memory standards are supported with just a simple BIOS microcode update to perhaps supply the proper base clock to memory frequency multipliers required.
  • With 3 memory channels per processor, each channel supports a maximum of 3 DIMMs. Do the math and a single processor can support a maximum of 9 memory slots. The minimum would however be three, one DIMM per channel. So depending on the motherboard class of use, the board can come configured with three, six or nine memory slots. However, Servers are generally at least 2-way SMP systems and with two Nehalem class processors, the total memory slots supported will double to 18!
  • Unlike Intel's FSB-based architecture where the chipset can be updated to support various memory standards, the integration of the DDR3 memory controller into CPU will mean that there will be a slower progression to adapt to newer memory standards, just like AMD's processors today. That's probably a downside that the industry as a whole will need to adjust accordingly.
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