Event Coverage

IDF Spring 2007 Update (Part 1)

By Dr. Jimmy Tang - 19 Apr 2007

Intel Xeon MP, Tolapai & Nehalem

Intel Xeon MP, Tolapai & Nehalem

Pat Gelsinger, Intel Senior Vice President and General Manager of the Digital Enterprise Group detailed upcoming products in the server segment during the morning keynote at IDF. He indicated that early Penryn performance were looking great and high-performance computing (HPC) and workstation systems can expect a significant boost to their performance, with gains up to an estimated 45 percent for bandwidth intensive applications and a 25 percent increase for servers using Java.

Gelsinger also talked about Intel's high-end quad and dual-core multi-processor servers which (codenamed Caneland) will be making its debut in the third quarter of this year. These new processors will complete the line-up of Intel's Xeon processors with support for multi-processor systems. The new Intel Xeon processor 7300 series will come in either 80 or 50 watt versions for blades.

 Caneland platform for the upcoming Intel Xeon processor 7300 series.

Intel also planned to release a highly integrated enterprise-class "system-on-chip" (SoC) product in 2008, codenamed Tolapai. The chip integrates several key components, such as an IA instruction set (an x86 processor), a memory controller and an I/O controller. It's basically a single chip that aims to help developers simplify system designs by reducing the chip footprint size by up to 45 percent and taking power consumption down by approximately 20 percent (as compared to a standard four-chip design). Also integrated with Tolapai is Intel's QuickAssist Technology which is a comprehensive accelerator initiative to optimize the use of accelerators in servers. Such accelerators benefit the system by optimizing the performance of certain functions, such as security encryption or financial computation. A general purpose x86 processor would not be able to handle such functions effectively and these accelerators would help boost the performance of the system while reducing power consumption.

 Expected performance gains and power/footprint reduction with Tolapai as compared with a four-chip design.

Gelsinger also talked about the next generation of processors with the codename Nehalem. These would be scheduled for 2008 and they will come with one to eight or more cores per product. Intel indicated that Nehalem would have some sort of hyper threading like features, with each core handling up to two threads at one time. Although details were sketchy, some of these Nehalem parts would contain components such as system interconnects, integrated memory controllers and even the option for a high-performance integrated graphics engine. Nehalem would be the chip that would significantly change the platform, judging from the initial specs released during IDF.

Going further ahead, Intel would journey into 32nm chips with Westmere in 2009 and Sandy Bridge in 2010. No details were released about these future processors, except for these codenames.

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