Justin Rattner's opening keynotes today was a half-hour run through on Intel's new focus on energy efficiency as evident in this year's theme of "Power-Optimized Platforms". Rattner talked about energy being the critical focus in Intel today, be it in high-density data centers, thin and light notebooks or even in handheld devices.
Parallels were drawn with the automotive industry, where there is an eternal power struggle between performance and energy consumption. You either have high-speed vehicles that guzzle fuel, or long distance fuel economy, but less-than exciting speeds. Rattner then revealed that Intel has been facing the same problems with microprocessor ramping, detailing how energy use has quadrupled over the past decade beginning from the original Pentium till today's Pentium 4. "Every increase in performance required an intended increase in energy expended", Rattner said. The new buzzword thrown about today was 'Energy-per-instruction' or the amount of energy required to execute a single instruction in a processor.
When Intel first introduced the Pentium M around 2003, they developed a mobile processor that was able to match the energy efficiency that the original Pentium exhibited back in 1993. Of course, we all know that mobile processors are unable to match the performance of desktop systems and Intel's deeply pipelined and power hungry NetBurst microarchitecture just went to prove that they were going the wrong way. This was one of the areas Intel has been facing tough challenges from AMD.
The push towards multi-core technologies and the launch of the Yonah (Core Duo) processor and Napa (Centrino Duo) platform were the first steps to delivering best-in-class performance with great energy savings. Today Rattner finally revealed the details about Intel's long talked about Next Generation Microarchitecture - what has now been christened as the Intel Core microarchitecture (somehow, we saw that coming). The Core microarchitecture will make its debut with the 65nm Merom, Conroe and Woodcrest processors by Q3 this year and will be the pervasive microarchitecture across all Intel platforms then.