2006 has already been earmarked as a very exciting year as far as the microprocessor industry is concerned. The heated battle by Intel and AMD will reach a new level as both companies are due to unleash microprocessor architectural and platform changes, some already much hyped about and some only talked behind closed doors. Intel is set to throw the first punches with their inaugural Spring Intel Developer Conference (IDF) in San Francisco and this year, we're going to hear a lot more about power optimizations and of course, Intel's Next Generation Micro-Architecture.
IDF Spring 2006 will actually mark a change from the past events as Intel cuts down the fats and focus more on the facts. There will only be a single day of keynotes covering the three main divisions from digital enterprise, home and mobility with an opening by Intel's CTO Justin Rattner. Intel also has streamlined their core tracks for the entire event so there should be much better access to information and more chances of hands-on experiences. While IDF Spring 2006 will officially kick-off tomorrow, Tuesday, 7th March, Intel held a pre-IDF activity today for international Press and analysts which focused on Intel's research and development efforts underway as well as bringing forward the Tech-a-Palooza panel highlighting the progress of some key Intel initiatives.
With the revised IDF agenda, this Day-0 event basically helps get the less important stuff (and by less important, we really mean the less juicy bits) out of the way. The opening briefing was also conducted by Justin Rattner, followed by talks on enterprise energy saving by Raj Yavatkar (Director, Systems Technology Lab) and the future of mobility by Kevin Kahn (Director, Communications Technology Lab). As you might have guessed, the R&D session skims through what Intel has been up to behind the scenes, besides putting out microprocessors and thinking up confusing naming schemes. Intel talked at length about their research activities and programs, but the highlights of the morning were the announcement of the Tera-Scale Computing Research Program, Transactional Memory, Seamless Access and Slicing-by-8.
During IDF Spring 2004, then Intel CTO Pat Gelsinger spoke about architecting the 'Era of Tera' in his keynote speech, whereby technology is moving at a pace where we'll soon be dealing with 'terabytes of data with teraflops of power'. The Intel Tera-Scale Computing Research Program is a huge effort within Intel's own worldwide research community to bring about platforms with 10's to 100's of cores (and there you thought dual core was hot). Intel already has over 80 projects ongoing into this effort that envelops silicon research, platform architecture and optimizations plus enabling highly threaded and scalable software models.
Of course all of these are still in their research phase, so expect to hear more about Tera-Scale efforts over the next few years. Since the scope of this project was a little too vast for our simple minds to comprehend, Intel gave a little example of intelligent vehicles; vehicles with enough compute power not only to be able to drive itself and navigate in traffic, but able to detect if the driver has fallen asleep and take over seamlessly. Or maybe even detect that the driver is sleepy and offer to switch to automatic drive. Sounds incredible? It may not be too far away. Intel-sponsored teams at the 2005 DARPA grand challenge won top three spots for completing a 132-mile race through the Mojave Desert by autonomous and unmanned robotic vehicles. The winner, 'Stanley', a modified Volkswagon Tuaureg designed by a Stanford University team used six Intel Pentium M processor-based computers for its AI.
Transactional Memory is actually a project that is part of the Tera-Scale Computing Research Program. Transactional memory is an effort to do away with memory locks that do not scale well with increasing parallelism and threading. In today's multi-threaded programming scenario, when a thread accesses common memory, that portion of memory and its data is locked for the period and other threads will just have to wait, reducing parallelism performance. Transactional Memory is a research into how Intel can coordinate a way for multiple threads to access the same memory, enable concurrent execution and without errors or deadlocks.
Intel used industry standard Java code to design a proof-of-concept application, which simulates in software how Transactional Memory technology delivers about triple the performance gain in an 8-threaded application.
As we move on to the mobility side of things, we hear about a technology called Seamless Access, which is basically Intel's effort into developing a unified architecture for public networks. Now before you think Seamless Access is intended to replace current network architectures or access modes, it isn't. Seamless Access is an open framework for network interoperability and is used to enable heterogeneous network roaming. If you're a frequent traveler and use multiple mobile or wireless devices, you'll most likely have experienced difficulty at some point or another trying to connect to foreign networks. Seamless Access aims to solve these. Intel has been working with telecoms and network industries to come up with a set of harmonized framework standards. Far from being 'just research', Seamless Access is already on the verge of being rolled out commercially in several countries, Singapore included. What's more, Intel has offered a live demo right here at IDF Spring 2006 with the first instance of Seamless Access roaming that supports both WiFi and 3G SIM authentication methods across various ISP networks around the IDF venues and participating hotels.
Unfortunately, SIM readers were rare and we were unable to procure one for testing the 3D SIM authentication method, but the WiFi login worked fine
In what may seem to be a weird name, Slicing-by-8 or SB8 is an exciting new CRC algorithm project, which has been in development by Intel and is now commercially available. We should all have heard of CRCs (Cyclic Redundancy Check) in some form or another as they are commonly used to check for data errors when files are transferred from one location to another. What you may not know is that traditional CRC methods actually incur a high processing overhead. This might not cause a problem with local file transfers, but CRC checking is a performance bottleneck with today's increasing speed of network pipelines, the emergence of high-speed SANs (Storage Area Networks) and iSCSI standards. Intel's SB8 algorithm is a new way of performing CRC with triple the speed of the older Sarwate method and is optimized for 64-bit operation and highly scalable with multi-core processors and frequency. What's more interesting is that SB8 is freely available through sourceforge.net. We did a check on its project page and it seems that Intel has only set it up about four days ago under a BSD license.
You've probably heard about Radio Free Intel, an initiative to integrate low-cost radio capabilities onto every silicon product Intel produces. Integrated radio is the next evolution of radio technology that would help reduce cost and increase battery performance and thermals to further advance mobile wireless communication. During Kevin Kahn's briefing, he talked about CMOS integration and even built a prototype CMOS MIMO device using a 90nm CMOS process. This prototype CMOS MIMO wireless chip is capable of up to 108Mbps and we have reason to believe that Intel may have this device on demonstration sometime during the length of this year's IDF. If we do come by it, rest assured we'd take a closer look.